The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.
Join the leading chiplet startup! As an Eliyan Staff DFT Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining and implementing scan, memory BIST, IEEE 1149.x/1687/1500/1838 structures, and reporting coverage. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:
- Work with the DFT and Chip Architects to define DFT strategy, methodologies, and implementation plan for various projects (chip_level and stand-alone IP blocks such as PHYs and chiplets)
- Implement DFT features in RTL for digital and analog blocks to the defined architecture & plan
- Generate patterns (e.g., 1687 PLDs, 1149.x, MBIST, etc.) and validate the same at the RTL & gate level
- Generate ATPG patterns (SA/TDF/etc.) and validate the same in 0-delay and SDF-delay based simulations.
- Collaborate with Analog/Mixed Signal (AMS) teams to ensure DFT coverage for high-speed interfaces & implement structural tests for digital logic in the analog blocks
- Work with circuit architects on advanced testing techniques such as PRBS-based PHY loopback capabilities, internal measurement of high-speed clock networks, etc.
- Support flow automation and scripting
- Support device bring up in the lab and pattern handoff to operations for high volume manufacturing and qualification (e.g., running patterns in the lab via the TAP controller, post-silicon bring up of patterns on the ATE, pattern bring up for HTOL and other QUAL activities, RMA analysis, etc.)
- Document overall test coverage and mitigation strategy to narrow down holes
Minimum Qualifications:
- Proficient in modern DFT/DFx techniques, methods, & tools (scan insert & ATPG, MBIST, etc.)
- Working knowledge of relevant industry standards (e.g., IEEE 1149.x/1687/1500/1838)
- Proficient in Verilog simulation & debug of DFT structures at the RTL & gate level
- General knowledge of digital and AMS circuit design techniques
- Experience in taping out at least 4 designs and bring up of at least 2 designs on an ATE or in the lab
- Proficient in TCL/shell scripting, working knowledge of scripting in one of perl/python or similar languages, working knowledge of other industry standard tools (Make, bug tracking, colab SW)
- Ability to work collaboratively with cross functional team
- BS EE or equivalent, with 6-9 years of experience
Ideal Qualifications:
- Deep expertise in modern test methods and DFx methodologies
- Experience in balancing tradeoffs of test time vs complexity (PPA) vs coverage
- Experience in taking a holistic view of a devices test coverage to incorporate the coverage from non-structural tests into the overall coverage analysis
- Experience with delivery of hard and soft IP to internal and external customers, including the ability to create design kit collaterals for the IP
- 3+ experience with Siemens Tessent platform including ATPG, MBIST, iJtag, BS, and SSN flows
- MS/PhD EE or equivalent, with 6-9 years of experience
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